In recent years, phase-change memories using chalcogenide materials as recording materials have been actively researched. Phase-change memory is a type of resistance random access memories that store information utilizing that the recording material between electrodes has different resistive states.
Phase-change memory stores information utilizing that the electric resistance of phase-change materials such as Ge2Sb2Te5 is different between the amorphous state and the crystal state. The resistance is high in the amorphous state and is low in the crystal state. Therefore, the information is read out from the memory by providing the both ends of the element with an electric voltage difference, by measuring the electric current flowing through the element, and by identifying the high resistance state/low resistance state of the element.
Phase-change memory rewrites data by changing the electric resistance of the phase-change film into different state using Joule heat generated by electric current. Reset operation, i.e. an operation changing the phase-change material into highly resistive amorphous state, is performed by causing a large current to flow for short time to melt the phase-change material, and then by rapidly decreasing the current to rapidly cool the phase-change material. On the other hand, set operation, i.e. an operation changing the phase-change material into lowly resistive crystal state, is performed by causing, for long time, an electric current to flow that is sufficient for keeping the phase-change material at the crystallization temperature. This phase-change memory requires smaller current to change the state of the phase-change film as the size of the memory is miniaturized. Thus it is theoretically suitable for miniaturization. Therefore, the phase-change memory has been actively researched.
Patent Literature 1 listed below describes, as a method for highly integrating a phase-change memory, a configuration where: in a stack structure in which multiple of gate electrode materials and insulator films are stacked alternately, multiple through holes penetrating all layers are formed by collective processing; a gate insulator film, a channel layer, and a phase-change film are formed inside the through hole. Each of the memory cells includes a transistor and a phase-change element connected in parallel. The memory cells are serially connected in the vertical direction, i.e. in the normal direction with respect to the semiconductor substrate, thereby forming a phase-change memory chain. In the array structure in Patent Literature 1, a vertical select transistor selects each of the phase-change memory chains. The channel semiconductor layer of each select transistor has a structure separated for each of the phase-change memory chains.
In the example described in Patent Literature 2 listed below, a diode is used instead of select transistor to select each phase-change memory chain. Patent Literature 2 also discloses a configuration where: when further stacking multiple phase-change chains, the electrode terminals are shared between resistance-change chains of each layer in order to suppress increase in number of terminals to which independent electric voltages are provided; only the gate terminal of the newly added layer select transistor is independently operated.